1. Field of the Invention
The invention relates to an interface circuit for transmitting and receiving a signal between two apparatuses which are driven by different power sources.
2. Related Background Art
FIG. 2 is a constructional diagram of a conventional ROM writing system including a ROM writing apparatus disclosed in Literature 1 (refer to “PW66K Flash Writer System—User's Manual”, Oki Electric Industry Co., Ltd., pages 6–8, May 19, 1999).
According to such a ROM writing system, a program or data which is sent from a host computer 1 is written into a flash memory built in a microcomputer 2a on a user board 2 and the system has a ROM writing apparatus 10. The host computer 1 and the ROM writing apparatus 10 are connected by, for example, a serial interface of the RS-232C standard. The ROM writing apparatus 10 is connected to a terminal on the side of the user board 2 by a probe via a probe cable.
The ROM writing apparatus 10 has a power unit 11 for generating a stable power voltage VCC of 5V (DC: direct current) from a voltage of 12V (DC) which is supplied from an AC (alternating current) adapter 3. An output side of the power unit 11 is connected to a power node NP. The power voltage VCC is applied from the power node NP to a control unit 12. Further, the ROM writing apparatus 10 has an interface unit (I/F) 13 for transmitting and receiving a signal between the control unit 12 and the microcomputer 2a on the user board 2.
The I/F 13 has 3-state buffers 13a, 13b, and 13c corresponding to the signals. The 3-state buffers 13a and 13b transmit a clock signal CK and write data WD which are outputted from the control unit 12 to the microcomputer 2a side. The 3-state buffer 13c receives data DAT which is read out from the microcomputer 2a and sends it to the control unit 12. When a signal which is inputted to a control terminal is at the high (“H”) level, each of the 3-state buffers 13a to 13c sends the signal at an input terminal to an output terminal. When the signal to the control terminal is at the low (“L”) level, each buffer sets the output terminal to a high impedance.
The control terminals of the 3-state buffers 13a to 13c are connected to the power node NP via pull-up resistors 14a to 14c, respectively, and controlled by the signal sent from the control unit 12. To prevent the control unit 12 from being broken by an abnormal input voltage, protective diodes 15 and 16 are connected to the output side of the 3-state buffer 13c so that they are connected to a ground voltage GND and the power voltage VCC in the opposite directions, respectively.
Further, to prevent an erroneous operation or the like that is caused by a difference between the power voltage VCC of the ROM writing apparatus 10 and a power voltage VTG (for example, 2 to 5 V) of the microcomputer side, the I/F 13 is driven by the power voltage VTG which is applied from a power unit 2b on the user board 2 side.
The power unit 2b of the user board 2 side generates the power voltage VTG which is necessary for the ordinary operation of the microcomputer 2a. As a high voltage VPP for writing data into the flash memory built in the microcomputer 2a, 12V (DC) which is supplied from the AC adaptor 3 to the ROM writing apparatus 10 is applied as it is.
In such a ROM writing system, the data which is written from the host computer 1 into the flash memory built in the microcomputer 2a is supplied to the control unit 12 of the ROM writing apparatus 10 via the RS-232C interface. The supplied data is converted into data in a format according to a writing procedure of the microcomputer 2a side by the control unit 12 and sent to the I/F 13 in accordance with a predetermined protocol. In the I/F 13, the supplied data is converted into a signal level corresponding to the power voltage VTG of the user board 2 side and outputted to the microcomputer 2a side via the probe cable. Thus, the data is written into the flash memory built in the microcomputer 2a. 
To check the data written into the flash memory, the data DAT read out from the microcomputer 2a is sent to the control unit 12 via the 3-state buffer 13c. In the control unit 12, the written data is compared with the read-out data and whether the data has correctly been written or not can be discriminated.
However, the conventional ROM writing system has the following problems.
FIG. 3 is an explanatory diagram of the problems in the conventional ROM writing system.
The ROM writing apparatus 10 and the user board 2 are connected by the probe cable. A power source of the user board 2 is inputted. When the power source of the ROM writing apparatus 10 is shut off (in a state where the AC adaptor 3 is removed) in a state where the data signal DAT at the “H” level is outputted from the user board 2, the I/F 13 generates heat and, depending on circumstances, a thermal breakdown occurs.
Such a phenomenon is caused because when the AC adaptor 3 is removed, the power voltage VCC is not applied to the power node NP, the protective diode 16 which is supposed to be connected in the reverse direction is connected in the forward direction, so that an output signal of the 3-state buffer 13c is fed back to the control terminal via the protective diode 16 and the pull-up resistor 14c. 
As shown in an example in FIG. 3, the 3-state buffer 13c has a power terminal VD, a ground terminal VS, an input terminal I, an output terminal O, and a control terminal C and is constructed by inverters 21 and 22, an NAND 23, an NOR 24, a PMOS 25, and an NMOS 26.
The control terminal C of the 3-state buffer 13c is connected to an input side of the inverter 21. An output side of the inverter 21 is connected to an input side of either the inverter 22 or the NAND 23. An output side of the inverter 22 is connected to one of input sides of the NOR 24. The input terminal I is connected to the other input side of each of the NAND 23 and the NOR 24. Output sides of the NAND 23 and the NOR 24 are connected to gates of the PMOS 25 and NMOS 26, respectively. Drains of the PMOS 25 and NMOS 26 are connected to the output terminal O.
In the interface by such a 3-state buffer 13c, in a state where the power voltage VCC (for example, 5V) is supplied to the power node NP, the power voltage VTG (for example, 5V) is applied from the user board 2 to the power terminal VD, and the data signal DAT at the “H” level is further inputted to the input terminal I, the signal at the output terminal O becomes almost the power voltage VTG.
When the AC adaptor 3 is removed here, the power voltage VCC which is supplied to the power node NP is extinguished. Thus, the “H” signal at the output terminal O of the 3-state buffer 13c is supplied to the control unit 12 via the protective diode 16 and the power node NP. Thus, a load current flows in the control unit 12 and an electric potential of the power node NP drops.
Although the electric potential of the power node NP is applied to the control terminal C of the 3-state buffer 13c via the pull-up resistor 14c, when the electric potential of the control terminal C becomes equal to almost ½ of the power voltage VTG, a pass current flows in a PMOS 21a and an NMOS 21b which construct the inverter 21. Thus, the phenomenon such that the I/F 13 generates the heat and, depending on circumstances, it results in the thermal breakdown occurs.